The present disclosure relates generally to computer systems, and more particularly to methods, systems, and computer program products of synchronous data input/output (I/O) system using prefetched device table entry.
For a computer system having multiple data storage devices, accessing data on these data storage devices takes time and resources. Conventionally, the computer system uses an asynchronous data I/O system. In the asynchronous data I/O system, when a processor of the computer system requests certain data from one of the storage devices, the storage device takes a certain amount of time to get the data back to the processor. Typically, the processor yields its processor power to other processes, programs, tasks, and/or threads while the processor waits for the data. Such an asynchronous data I/O system is inefficient. In order to increase the efficiency of data I/O, a synchronous data I/O system may be used. The synchronous data I/O system retrieves data from the storage devices faster in comparison since the processor does wait for the data, and in turn may not share processing power with the other processes, programs, tasks, and/or threads.
Typically, the synchronous data I/O system fetches a dedicated device table entry (DTE) for each transaction. For example, the dedicated DTE is fetched from memory at the start of the transaction. Typically, the processor uses direct memory access (DMA) to access the DTE, which causes the processor to wait until a response arrives before making progress. Such delays associated with the DMA apply to each transaction. In addition, in order to guarantee peripheral component interconnect Express (PCIe) ordering rules, a host bridge stalls all incoming data traffic until the fetching of the DTE is completed and the fetching response arrives. Thus, depending on the latency within the memory subsystem, the latency for the affected transactions increases, for example by 100 ns-500 ns. In turn, the latencies of subsequent transactions increase similarly leading to a gap in the data flow, and limiting bandwidth. Thus, it is desirable to eliminate the gap in the data flow to improve efficiency of the synchronous I/O and consequently the computer system.
Therefore, heretofore unaddressed needs still exist in the art to address the aforementioned deficiencies and inadequacies.